/*
 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2021-2022. All rights reserved.
 * Description:  Interrupt DRIVER
 *
 * Create: 2021-10-13
 */
#include "stdint.h"
#include "chip_core_irq.h"
#if defined(__LITEOS__)
#include "los_hwi.h"
#elif defined(__FREERTOS__)
#include "FreeRTOS.h"
#include "hwi.h"
#elif defined(__ALIOS__)
#include "hwi_irq.h"
#endif

const uint8_t m_auc_int_pri[BUTT_IRQN] = {
#if defined(__LITEOS__)
    LOSCFG_HWI_PRIO_LIMIT,   // USER_SOFTWARE_INT_IRQn            = 0,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_SOFTWARE_INT_IRQn      = 1,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT2_IRQn                = 2,
    LOSCFG_HWI_PRIO_LIMIT,      // MACHINE_SOFTWARE_INT_IRQn         = 3,
    LOSCFG_HWI_PRIO_LIMIT,   // USER_TIMER_INT_IRQn               = 4,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_TIMER_INT_IRQn         = 5,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT6_IRQn                = 6,
    LOSCFG_HWI_PRIO_LIMIT,   // MACHINE_TIMER_INT_IRQn            = 7,
    LOSCFG_HWI_PRIO_LIMIT,   // USER_EXTERNAL_INT_IRQn            = 8,
    LOSCFG_HWI_PRIO_LIMIT,   // SUPERVISOR_EXTERNAL_INT_IRQn      = 9,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT10_IRQn               = 10,
    OS_HWI_PRIO_LOWEST,      // MACHINE_EXTERNAL_INT_IRQn         = 11,
    OS_HWI_PRIO_HIGHEST,     // NON_MASKABLE_INT_IRQn             = 12,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT13_IRQn               = 13,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT14_IRQn               = 14,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT15_IRQn               = 15,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT16_IRQn               = 16,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT17_IRQn               = 17,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT18_IRQn               = 18,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT19_IRQn               = 19,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT20_IRQn               = 20,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT21_IRQn               = 21,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT22_IRQn               = 22,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT23_IRQn               = 23,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT24_IRQn               = 23,
    LOSCFG_HWI_PRIO_LIMIT,   // RESERVED_INT25_IRQn               = 25,

    OS_HWI_PRIO_LOWEST,      // RESERVED_INT0_IRQn                =  0,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT1_IRQn                =  1,
    OS_HWI_PRIO_LOWEST - 1,  // MCU_INT0_IRQN                     =  2,
    OS_HWI_PRIO_LOWEST,      // MCU_INT1_IRQN                     =  3,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT4_IRQn                =  4,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT5_IRQn                =  5,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT6_IRQn                =  6,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT7_IRQn                =  7,
    OS_HWI_PRIO_LOWEST,      // GPIO_0_IRQN                       =  8,
    OS_HWI_PRIO_LOWEST,      // GPIO_1_IRQN                       =  9,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT10_IRQn               = 10,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT11_IRQn               = 11,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT12_IRQn               = 12,
    OS_HWI_PRIO_LOWEST,      // UART_L0_IRQn                      = 13,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT14_IRQn               = 14,
    OS_HWI_PRIO_LOWEST - 2,  // UART_H0_IRQn                      = 15,
    OS_HWI_PRIO_LOWEST,      // UART_H1_IRQn                      = 16,
    OS_HWI_PRIO_LOWEST,      // QSPI0_2CS_IRQN                    = 17,
    OS_HWI_PRIO_LOWEST,      // QSPI1_2CS_IRQN                    = 18,
    OS_HWI_PRIO_LOWEST,      // SPI4_S_IRQN                       = 19,
    OS_HWI_PRIO_LOWEST - 1,  // KEY_SCAN_IRQN                     = 20,
    OS_HWI_PRIO_LOWEST - 1,  // M_WAKEUP_IRQN                     = 21,
    OS_HWI_PRIO_LOWEST,      // M_SLEEP_IRQN                      = 22,
    OS_HWI_PRIO_LOWEST,      // RTC_0_IRQN                        = 23,
    OS_HWI_PRIO_LOWEST,      // RTC_1_IRQN                        = 24,
    OS_HWI_PRIO_LOWEST,      // RTC_2_IRQN                        = 25,
    OS_HWI_PRIO_LOWEST,      // RTC_3_IRQN                        = 26,
    OS_HWI_PRIO_LOWEST - 1,  // TIMER_0_IRQN                      = 27,
    OS_HWI_PRIO_LOWEST - 1,  // TIMER_1_IRQN                      = 28,
    OS_HWI_PRIO_LOWEST - 1,  // TIMER_2_IRQN                      = 29,
    OS_HWI_PRIO_LOWEST,      // TIMER_3_IRQN                      = 30,
    OS_HWI_PRIO_LOWEST,      // M_SDMA_IRQN                       = 31,
    OS_HWI_PRIO_LOWEST,      // M_DMA_IRQN                        = 32,
    OS_HWI_PRIO_LOWEST,      // SPI_M_S_0_IRQN                    = 33,
    OS_HWI_PRIO_LOWEST,      // SPI_M_S_1_IRQN                    = 34,
    OS_HWI_PRIO_LOWEST,      // SPI_M_IRQN                        = 35,
    OS_HWI_PRIO_LOWEST,      // I2C_0_IRQN                        = 36,
    OS_HWI_PRIO_LOWEST,      // I2C_1_IRQN                        = 37,
    OS_HWI_PRIO_LOWEST,      // I2C_2_IRQN                        = 38,
    OS_HWI_PRIO_LOWEST,      // SPI3_MS_IRQN                      = 39,
    OS_HWI_PRIO_LOWEST,      // EFLASH_INT_IRQN                   = 40,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT41_IRQn               = 41,
    OS_HWI_PRIO_LOWEST - 3,  // RESERVED_INT42_IRQn               = 42,
    OS_HWI_PRIO_LOWEST,      // RESERVED_INT43_IRQn               = 43,
    OS_HWI_PRIO_LOWEST,      // SEC_INT_IRQN                      = 44,
    OS_HWI_PRIO_LOWEST,      // PWM_0_IRQN                        = 45,
    OS_HWI_PRIO_LOWEST,      // PWM_1_IRQN                        = 46
#elif defined(__FREERTOS__)
    configHWI_PRIO_LIMIT,   // USER_SOFTWARE_INT_IRQn            = 0,
    configHWI_PRIO_LIMIT,   // SUPERVISOR_SOFTWARE_INT_IRQn      = 1,
    configHWI_PRIO_LIMIT,   // RESERVED_INT2_IRQn                = 2,
    configHWI_PRIO_LIMIT,   // MACHINE_SOFTWARE_INT_IRQn      = 3,
    configHWI_PRIO_LIMIT,   // USER_TIMER_INT_IRQn               = 4,
    configHWI_PRIO_LIMIT,   // SUPERVISOR_TIMER_INT_IRQn         = 5,
    configHWI_PRIO_LIMIT,   // RESERVED_INT6_IRQn                = 6,
    configHWI_PRIO_LIMIT,   // MACHINE_TIMER_INT_IRQn            = 7,
    configHWI_PRIO_LIMIT,   // USER_EXTERNAL_INT_IRQn            = 8,
    configHWI_PRIO_LIMIT,   // SUPERVISOR_EXTERNAL_INT_IRQn      = 9,
    configHWI_PRIO_LIMIT,   // RESERVED_INT10_IRQn               = 10,
    configHWI_PRIO_LOWEST,  // MACHINE_EXTERNAL_INT_IRQn         = 11,
    configHWI_PRIO_HIGHEST, // NON_MASKABLE_INT_IRQn             = 12,
    configHWI_PRIO_LIMIT,   // RESERVED_INT13_IRQn               = 13,
    configHWI_PRIO_LIMIT,   // RESERVED_INT14_IRQn               = 14,
    configHWI_PRIO_LIMIT,   // RESERVED_INT15_IRQn               = 15,
    configHWI_PRIO_LIMIT,   // RESERVED_INT16_IRQn               = 16,
    configHWI_PRIO_LIMIT,   // RESERVED_INT17_IRQn               = 17,
    configHWI_PRIO_LIMIT,   // RESERVED_INT18_IRQn               = 18,
    configHWI_PRIO_LIMIT,   // RESERVED_INT19_IRQn               = 19,
    configHWI_PRIO_LIMIT,   // RESERVED_INT20_IRQn               = 20,
    configHWI_PRIO_LIMIT,   // RESERVED_INT21_IRQn               = 21,
    configHWI_PRIO_LIMIT,   // RESERVED_INT22_IRQn               = 22,
    configHWI_PRIO_LIMIT,   // RESERVED_INT23_IRQn               = 23,
    configHWI_PRIO_LIMIT,   // RESERVED_INT24_IRQn               = 23,
    configHWI_PRIO_LIMIT,   // RESERVED_INT25_IRQn               = 25,

    configHWI_PRIO_LOWEST,      // RESERVED_INT0_IRQn                =  0,
    configHWI_PRIO_LOWEST,      // RESERVED_INT1_IRQn                =  1,
    configHWI_PRIO_LOWEST - 1,  // MCU_INT0_IRQN                     =  2,
    configHWI_PRIO_LOWEST,      // MCU_INT1_IRQN                     =  3,
    configHWI_PRIO_LOWEST,      // RESERVED_INT4_IRQn                =  4,
    configHWI_PRIO_LOWEST,      // RESERVED_INT5_IRQn                =  5,
    configHWI_PRIO_LOWEST,      // RESERVED_INT6_IRQn                =  6,
    configHWI_PRIO_LOWEST,      // RESERVED_INT7_IRQn                =  7,
    configHWI_PRIO_LOWEST,      // GPIO_0_IRQN                       =  8,
    configHWI_PRIO_LOWEST,      // GPIO_1_IRQN                       =  9,
    configHWI_PRIO_LOWEST,      // RESERVED_INT10_IRQn               = 10,
    configHWI_PRIO_LOWEST,      // RESERVED_INT11_IRQn               = 11,
    configHWI_PRIO_LOWEST,      // RESERVED_INT12_IRQn               = 12,
    configHWI_PRIO_LOWEST,      // UART_L0_IRQn                      = 13,
    configHWI_PRIO_LOWEST,      // RESERVED_INT14_IRQn               = 14,
    configHWI_PRIO_LOWEST - 2,  // UART_H0_IRQn                      = 15,
    configHWI_PRIO_LOWEST,      // UART_H1_IRQn                      = 16,
    configHWI_PRIO_LOWEST,      // QSPI0_2CS_IRQN                    = 17,
    configHWI_PRIO_LOWEST,      // QSPI1_2CS_IRQN                    = 18,
    configHWI_PRIO_LOWEST,      // SPI4_S_IRQN                       = 19,
    configHWI_PRIO_LOWEST - 1,  // KEY_SCAN_IRQN                     = 20,
    configHWI_PRIO_LOWEST - 1,  // M_WAKEUP_IRQN                     = 21,
    configHWI_PRIO_LOWEST,      // M_SLEEP_IRQN                      = 22,
    configHWI_PRIO_LOWEST,      // RTC_0_IRQN                        = 23,
    configHWI_PRIO_LOWEST,      // RTC_1_IRQN                        = 24,
    configHWI_PRIO_LOWEST,      // RTC_2_IRQN                        = 25,
    configHWI_PRIO_LOWEST,      // RTC_3_IRQN                        = 26,
    configHWI_PRIO_LOWEST - 1,  // TIMER_0_IRQN                      = 27,
    configHWI_PRIO_LOWEST - 1,  // TIMER_1_IRQN                      = 28,
    configHWI_PRIO_LOWEST - 1,  // TIMER_2_IRQN                      = 29,
    configHWI_PRIO_LOWEST,      // TIMER_3_IRQN                      = 30,
    configHWI_PRIO_LOWEST,      // M_SDMA_IRQN                       = 31,
    configHWI_PRIO_LOWEST,      // M_DMA_IRQN                        = 32,
    configHWI_PRIO_LOWEST,      // SPI_M_S_0_IRQN                    = 33,
    configHWI_PRIO_LOWEST,      // SPI_M_S_1_IRQN                    = 34,
    configHWI_PRIO_LOWEST,      // SPI_M_IRQN                        = 35,
    configHWI_PRIO_LOWEST,      // I2C_0_IRQN                        = 36,
    configHWI_PRIO_LOWEST,      // I2C_1_IRQN                        = 37,
    configHWI_PRIO_LOWEST,      // I2C_2_IRQN                        = 38,
    configHWI_PRIO_LOWEST,      // SPI3_MS_IRQN                      = 39,
    configHWI_PRIO_LOWEST,      // EFLASH_INT_IRQN                   = 40,
    configHWI_PRIO_LOWEST,      // RESERVED_INT41_IRQn               = 41,
    configHWI_PRIO_LOWEST - 3,  // RESERVED_INT42_IRQn               = 42,
    configHWI_PRIO_LOWEST,      // RESERVED_INT43_IRQn               = 43,
    configHWI_PRIO_LOWEST,      // SEC_INT_IRQN                      = 44,
    configHWI_PRIO_LOWEST,      // PWM_0_IRQN                        = 45,
    configHWI_PRIO_LOWEST,      // PWM_1_IRQN                        = 46
#elif defined(__ALIOS__)
    HWI_PRIO_LIMIT,   // USER_SOFTWARE_INT_IRQn            = 0,
    HWI_PRIO_LIMIT,   // SUPERVISOR_SOFTWARE_INT_IRQn      = 1,
    HWI_PRIO_LIMIT,   // RESERVED_INT2_IRQn                = 2,
    HWI_PRIO_LIMIT,   // MACHINE_SOFTWARE_INT_IRQn      = 3,
    HWI_PRIO_LIMIT,   // USER_TIMER_INT_IRQn               = 4,
    HWI_PRIO_LIMIT,   // SUPERVISOR_TIMER_INT_IRQn         = 5,
    HWI_PRIO_LIMIT,   // RESERVED_INT6_IRQn                = 6,
    HWI_PRIO_LIMIT,   // MACHINE_TIMER_INT_IRQn            = 7,
    HWI_PRIO_LIMIT,   // USER_EXTERNAL_INT_IRQn            = 8,
    HWI_PRIO_LIMIT,   // SUPERVISOR_EXTERNAL_INT_IRQn      = 9,
    HWI_PRIO_LIMIT,   // RESERVED_INT10_IRQn               = 10,
    HWI_PRIO_LOWEST,  // MACHINE_EXTERNAL_INT_IRQn         = 11,
    HWI_PRIO_HIGHEST, // NON_MASKABLE_INT_IRQn             = 12,
    HWI_PRIO_LIMIT,   // RESERVED_INT13_IRQn               = 13,
    HWI_PRIO_LIMIT,   // RESERVED_INT14_IRQn               = 14,
    HWI_PRIO_LIMIT,   // RESERVED_INT15_IRQn               = 15,
    HWI_PRIO_LIMIT,   // RESERVED_INT16_IRQn               = 16,
    HWI_PRIO_LIMIT,   // RESERVED_INT17_IRQn               = 17,
    HWI_PRIO_LIMIT,   // RESERVED_INT18_IRQn               = 18,
    HWI_PRIO_LIMIT,   // RESERVED_INT19_IRQn               = 19,
    HWI_PRIO_LIMIT,   // RESERVED_INT20_IRQn               = 20,
    HWI_PRIO_LIMIT,   // RESERVED_INT21_IRQn               = 21,
    HWI_PRIO_LIMIT,   // RESERVED_INT22_IRQn               = 22,
    HWI_PRIO_LIMIT,   // RESERVED_INT23_IRQn               = 23,
    HWI_PRIO_LIMIT,   // RESERVED_INT24_IRQn               = 23,
    HWI_PRIO_LIMIT,   // RESERVED_INT25_IRQn               = 25,

    HWI_PRIO_LOWEST,      // RESERVED_INT0_IRQn                =  0,
    HWI_PRIO_LOWEST,      // RESERVED_INT1_IRQn                =  1,
    HWI_PRIO_LOWEST - 1,  // MCU_INT0_IRQN                     =  2,
    HWI_PRIO_LOWEST,      // MCU_INT1_IRQN                     =  3,
    HWI_PRIO_LOWEST,      // RESERVED_INT4_IRQn                =  4,
    HWI_PRIO_LOWEST,      // RESERVED_INT5_IRQn                =  5,
    HWI_PRIO_LOWEST,      // RESERVED_INT6_IRQn                =  6,
    HWI_PRIO_LOWEST,      // RESERVED_INT7_IRQn                =  7,
    HWI_PRIO_LOWEST,      // GPIO_0_IRQN                       =  8,
    HWI_PRIO_LOWEST,      // GPIO_1_IRQN                       =  9,
    HWI_PRIO_LOWEST,      // RESERVED_INT10_IRQn               = 10,
    HWI_PRIO_LOWEST,      // RESERVED_INT11_IRQn               = 11,
    HWI_PRIO_LOWEST,      // RESERVED_INT12_IRQn               = 12,
    HWI_PRIO_LOWEST,      // UART_L0_IRQn                      = 13,
    HWI_PRIO_LOWEST,      // RESERVED_INT14_IRQn               = 14,
    HWI_PRIO_LOWEST - 2,  // UART_H0_IRQn                      = 15,
    HWI_PRIO_LOWEST,      // UART_H1_IRQn                      = 16,
    HWI_PRIO_LOWEST,      // QSPI0_2CS_IRQN                    = 17,
    HWI_PRIO_LOWEST,      // QSPI1_2CS_IRQN                    = 18,
    HWI_PRIO_LOWEST,      // SPI4_S_IRQN                       = 19,
    HWI_PRIO_LOWEST - 1,  // KEY_SCAN_IRQN                     = 20,
    HWI_PRIO_LOWEST - 1,  // M_WAKEUP_IRQN                     = 21,
    HWI_PRIO_LOWEST,      // M_SLEEP_IRQN                      = 22,
    HWI_PRIO_LOWEST,      // RTC_0_IRQN                        = 23,
    HWI_PRIO_LOWEST,      // RTC_1_IRQN                        = 24,
    HWI_PRIO_LOWEST,      // RTC_2_IRQN                        = 25,
    HWI_PRIO_LOWEST,      // RTC_3_IRQN                        = 26,
    HWI_PRIO_LOWEST - 1,  // TIMER_0_IRQN                      = 27,
    HWI_PRIO_LOWEST - 1,  // TIMER_1_IRQN                      = 28,
    HWI_PRIO_LOWEST - 1,  // TIMER_2_IRQN                      = 29,
    HWI_PRIO_LOWEST,      // TIMER_3_IRQN                      = 30,
    HWI_PRIO_LOWEST,      // M_SDMA_IRQN                       = 31,
    HWI_PRIO_LOWEST,      // M_DMA_IRQN                        = 32,
    HWI_PRIO_LOWEST,      // SPI_M_S_0_IRQN                    = 33,
    HWI_PRIO_LOWEST,      // SPI_M_S_1_IRQN                    = 34,
    HWI_PRIO_LOWEST,      // SPI_M_IRQN                        = 35,
    HWI_PRIO_LOWEST,      // I2C_0_IRQN                        = 36,
    HWI_PRIO_LOWEST,      // I2C_1_IRQN                        = 37,
    HWI_PRIO_LOWEST,      // I2C_2_IRQN                        = 38,
    HWI_PRIO_LOWEST,      // SPI3_MS_IRQN                      = 39,
    HWI_PRIO_LOWEST,      // EFLASH_INT_IRQN                   = 40,
    HWI_PRIO_LOWEST,      // RESERVED_INT41_IRQn               = 41,
    HWI_PRIO_LOWEST - 3,  // RESERVED_INT42_IRQn               = 42,
    HWI_PRIO_LOWEST,      // RESERVED_INT43_IRQn               = 43,
    HWI_PRIO_LOWEST,      // SEC_INT_IRQN                      = 44,
    HWI_PRIO_LOWEST,      // PWM_0_IRQN                        = 45,
    HWI_PRIO_LOWEST,      // PWM_1_IRQN                        = 46
#endif
};
